The DDR3 Controller V2 core is a pre-designed, reusable hardware block that integrates a high-speed interface between an internal processing system and external DDR3 SDRAM memory. The DDR3 Controller V2 core handles the DDR-related timing parameters, the priority queue, and other memory operations with external memory.

DDR3 Controller V2 Core Block Diagram

Features

The DDR3 Controller V2 core includes the following features:

• Complies with JEDEC's JESD79-3F specification
• x8 DDR3/DDRL
• Speed of up to 1,333 Mbps (1)
• Supports memory sizes of 512 MB, 1 GB, 2 GB, 4 GB, and 8 GB
• Power-down feature
• Supports recalibration
• Native user interface
• 64-bit user interface bit width for x8 operation mode
• Interface with the enhanced FPGA-hardened HSIO2